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PIC10F200-I/P 参数 Datasheet PDF下载

PIC10F200-I/P图片预览
型号: PIC10F200-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 6引脚8位闪存微控制器 [6-Pin, 8-Bit Flash Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 96 页 / 1447 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC10F200/202/204/206  
9.6.1  
WDT PERIOD  
9.5  
Device Reset Timer (DRT)  
The WDT has a nominal time-out period of 18 ms, (with  
no prescaler). If a longer time-out period is desired, a  
prescaler with a division ratio of up to 1:128 can be  
assigned to the WDT (under software control) by  
writing to the OPTION register. Thus, a time-out period  
of a nominal 2.3 seconds can be realized. These peri-  
ods vary with temperature, VDD and part-to-part  
process variations (see DC specs).  
On the PIC10F200/202/204/206 devices, the DRT runs  
any time the device is powered up.  
The DRT operates on an internal oscillator. The  
processor is kept in Reset as long as the DRT is active.  
The DRT delay allows VDD to rise above VDD min. and  
for the oscillator to stabilize.  
The on-chip DRT keeps the devices in a Reset  
condition for approximately 18 ms after MCLR has  
reached a logic high (VIH MCLR) level. Programming  
GP3/MCLR/VPP as MCLR and using an external RC  
network connected to the MCLR input is not required in  
most cases. This allows savings in cost-sensitive and/  
or space restricted applications, as well as allowing the  
use of the GP3/MCLR/VPP pin as a general purpose  
input.  
Under worst-case conditions (VDD = Min., Temperature  
= Max., max. WDT prescaler), it may take several  
seconds before a WDT time-out occurs.  
9.6.2  
WDT PROGRAMMING  
CONSIDERATIONS  
The CLRWDT instruction clears the WDT and the  
postscaler, if assigned to the WDT, and prevents it from  
timing out and generating a device Reset.  
The Device Reset Time delays will vary from chip-to-  
chip due to VDD, temperature and process variation.  
See AC parameters for details.  
The SLEEP instruction resets the WDT and the  
postscaler, if assigned to the WDT. This gives the  
maximum Sleep time before a WDT wake-up Reset.  
Reset sources are POR, MCLR, WDT time-out and  
wake-up on pin change. See Section 9.9.2 “Wake-up  
from Sleep”, Notes 1, 2 and 3.  
TABLE 9-3:  
DRT (DEVICE RESET TIMER  
PERIOD)  
Subsequent  
POR Reset  
Oscillator  
Resets  
INTOSC  
18 ms (typical) 10 μs (typical)  
9.6  
Watchdog Timer (WDT)  
The Watchdog Timer (WDT) is a free running on-chip  
RC oscillator, which does not require any external  
components. This RC oscillator is separate from the  
internal 4 MHz oscillator. This means that the WDT will  
run even if the main processor clock has been stopped,  
for example, by execution of a SLEEP instruction.  
During normal operation or Sleep, a WDT Reset or  
wake-up Reset, generates a device Reset.  
The TO bit (STATUS<4>) will be cleared upon a  
Watchdog Timer Reset.  
The WDT can be permanently disabled by program-  
ming the configuration WDTE as a ‘0’ (see Section 9.1  
“Configuration Bits”). Refer to the PIC10F200/202/  
204/206 Programming Specifications to determine how  
to access the Configuration Word.  
DS41239D-page 46  
© 2007 Microchip Technology Inc.  
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