PIC10F200/202/204/206
4.0
MEMORY ORGANIZATION
FIGURE 4-1:
The PIC10F200/202/204/206 memories are organized
into program memory and data memory. Data memory
banks are accessed using the File Select Register
(FSR).
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC10F200/204
PC<7:0>
9
Stack Level 1
Stack Level 2
CALL, RETLW
4.1
Program Memory Organization for
the PIC10F200/204
The PIC10F200/204 devices have a 9-bit Program
Counter (PC) capable of addressing a 512 x 12
program memory space.
Only the first 256 x 12 (0000h-00FFh) for the
PIC10F200/204 are physically implemented (see
boundaries will cause a wraparound within the first
256 x 12 space (PIC10F200/204). The effective
Reset vector is at 0000h (see Figure 4-1). Location
00FFh (PIC10F200/204) contains the internal clock
oscillator calibration value. This value should never
be overwritten.
Reset Vector
(1)
On-chip Program
Memory
User Memory
Space
0000h
256 Word
00FFh
0100h
01FFh
Note 1:
Address 0000h becomes the
effective Reset vector. Location
00FFh contains the
MOVLW XX
internal oscillator calibration value.
©
2007 Microchip Technology Inc.
DS41239D-page 15
MICROCHIP [ MICROCHIP TECHNOLOGY ]
