MCP6021/1R/2/3/4
After selecting R
ISO
for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
’s value until the
response is reasonable. Evaluation on the bench and
simulations with the MCP6021/1R/2/3/4 Spice macro
model are helpful.
4.5
MCP6023 Chip Select (CS)
4.4
Gain Peaking
Figure 2-35 and Figure 2-36 use R
F
= 1 kΩ to avoid
(frequency response) gain peaking and (step
response) overshoot. The capacitance to ground at the
inverting input (C
G
) is the op amp’s common mode
input capacitance plus board parasitic capacitance. C
G
is in parallel with R
G
, which causes an increase in gain
at high frequencies for non-inverting gains greater than
1 V/V (unity gain). C
G
also reduces the phase margin
of the feedback loop for both non-inverting and
inverting gains.
The MCP6023 is a single amplifier with chip select
(CS). When CS is high, the supply current is less than
10 nA (typ) and travels from the CS pin to V
SS
, with the
amplifier output being put into a high-impedance state.
When CS is low, the amplifier is enabled. If CS is left
floating, the amplifier may not operate properly.
Figure 1-1 and Figure 2-39 show the output voltage
and supply current response to a CS pulse.
4.6
MCP6021 and MCP6023 Reference
Voltage
V
IN
V
OUT
The single op amps (MCP6021 and MCP6023), not in
the SOT-23-5 package, have an internal mid-supply
reference voltage connected to the V
REF
pin (see
Figure 4-6). The MCP6021 has CS internally tied to
V
SS
, which always keeps the op amp on and always
provides a mid-supply reference. With the MCP6023,
taking the CS pin high conserves power by shutting
down both the op amp and the V
REF
circuitry. Taking
the CS pin low turns on the op amp and V
REF
circuitry.
V
DD
C
G
R
F
R
G
V
REF
50 kΩ
FIGURE 4-4:
Non-inverting gain circuit
with parasitic capacitance.
The largest value of R
F
in Figure 4-4 that should be
used is a function of noise gain (see G
N
in
Section 4.3
“Capacitive Loads”)
and C
G
. Figure 4-5 shows results
for various conditions. Other compensation techniques
may be used, but they tend to be more complicated to
the design.
1.E+05
100k
G
N
> +1 V/V
50 kΩ
CS
V
SS
(CS tied internally to V
SS
for MCP6021)
FIGURE 4-6:
Simplified internal V
REF
circuit (MCP6021 and MCP6023 only).
See Figure 4-7 for a non-inverting gain circuit using the
internal mid-supply reference. The DC-blocking
capacitor (C
B
) also reduces noise by coupling the op
amp input to the source.
C
G
= 50 pF
C
G
= 100 pF
Maximum R
F
(
Ω
)
10k
1.E+04
C
G
= 7 pF
C
G
= 20 pF
1k
1.E+03
R
G
R
F
100
1.E+02
1
Noise Gain; G
N
(V/V)
10
V
OUT
C
B
V
IN
V
REF
FIGURE 4-5:
Non-inverting gain circuit
with parasitic capacitance.
FIGURE 4-7:
Non-inverting gain circuit
using V
REF
(MCP6021 and MCP6023 only).
DS21685C-page 14
©
2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
