MCP6021/1R/2/3/4
4.0
APPLICATIONS INFORMATION
4.2
Rail-to-Rail Output
The MCP6021/1R/2/3/4 family of operational amplifiers
are fabricated on Microchip’s state-of-the-art CMOS
process. They are unity-gain stable and suitable for a
wide range of general-purpose applications.
The Maximum Output Voltage Swing is the maximum
swing possible under a particular output load.
According to the specification table, the output can
reach within 20 mV of either supply rail when
R
L
= 10 kΩ. See Figure 2-31 and Figure 2-34 for more
information concerning typical performance.
4.1
Rail-to-Rail Input
The MCP6021/1R/2/3/4 amplifier family is designed to
not exhibit phase inversion when the input pins exceed
the supply voltages. Figure 2-27 shows an input volt-
age exceeding both supplies with no resulting phase
inversion.
The input stage of the MCP6021/1R/2/3/4 family of
devices uses two differential input stages in parallel;
one operates at low common-mode input voltage
(V
CM
), while the other operates at high V
CM
. With this
topology, the device operates with V
CM
up to 0.3V past
either supply rail (V
SS
– 0.3V to V
DD
+ 0.3V) at +25°C.
The amplifier input behaves linearly as long as V
CM
is
kept within the specified V
CMR
limits. The input offset
voltage is measured at both V
CM
= V
SS
– 0.3V and
V
DD
+ 0.3V to ensure proper operation.
Input voltages that exceed the input voltage range
(V
CMR
) can cause excessive current to flow in or out of
the input pins. Current beyond ±2 mA introduces
possible reliability problems. Thus, applications that
exceed this rating must externally limit the input current
with an input resistor (R
IN
), as shown in Figure 4-1.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed loop bandwidth is
reduced. This produces gain-peaking in the frequency
response, with overshoot and ringing in the step
response.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (R
ISO
in Figure 4-2) improves the
feedback loop’s phase margin (stability) by making the
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
V
IN
MCP602X
R
ISO
V
OUT
C
L
R
IN
V
IN
MCP602X
V
OUT
FIGURE 4-2:
Output resistor R
ISO
stabilizes large capacitive loads.
Figure 4-3 gives recommended R
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit’s noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
1,000
Recommended R
ISO
(
Ω
)
G
N
≥
+1
R
IN
≥
R
IN
≥
(Maximum expected
V
IN
) -
V
DD
2 mA
V
SS
- (Minimum expected
V
IN
)
2 mA
FIGURE 4-1:
into an input pin.
R
IN
limits the current flow
Total Harmonic Distortion Plus Noise (THD+N) can be
affected by the common mode input voltage (V
CM
). As
shown in Figure 2-3 and Figure 2-6, the input offset
voltage (V
OS
) is affected by the change from the NMOS
to the PMOS input differential pairs. This change in V
OS
will increase the distortion if the input voltage includes
this transition region. This transition occurs between
V
DD
– 1.0V and V
DD
– 2.0V, depending on V
DD
and
temperature.
100
10
10
100
1,000
10,000
Normalized Capacitance; C
L
/G
N
(pF)
FIGURE 4-3:
Recommended R
ISO
values
for capacitive loads.
©
2006 Microchip Technology Inc.
DS21685C-page 13
MICROCHIP [ MICROCHIP TECHNOLOGY ]
