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MCP6002T-I/SN 参数 Datasheet PDF下载

MCP6002T-I/SN图片预览
型号: MCP6002T-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆赫,低功耗运算放大器 [1 MHz, Low-Power Op Amp]
分类和应用: 运算放大器
文件页数/大小: 28 页 / 455 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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MCP6001/2/4
ISO
values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
L
/G
N
), where G
N
is the
circuit's noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
1000
Recommended R
ISO
( )
4.5
PCB Surface Leakage
V
DD
= 5.0V
R
L
= 100 k
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
12
Ω.
A 5V difference would
cause 5 pA of current to flow; which is greater than the
MCP6001/2/4 family’s bias current at 25°C (1 pA, typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
V
IN
-
V
IN
+
V
SS
100
G
N
= 1
G
N
2
10
100p
1n
10n
10p
10n
1.E-11
1.E-10
1.E-09
1.E-08
Normalized Load Capacitance; C
L
/G
N
(F)
FIGURE 4-4:
Recommended R
ISO
values
for Capacitive Loads.
After selecting R
ISO
for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
’s value until the
response is reasonable. Bench evaluation and simula-
tions with the MCP6001/2/4 SPICE macro model are
very helpful.
Guard Ring
FIGURE 4-5:
for Inverting Gain.
1.
Example Guard Ring Layout
4.4
Supply Bypass
With this family of operational amplifiers, the power
supply pin (V
DD
for single-supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other analog parts.
2.
Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (V
IN
+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (V
IN
–). This biases the guard ring to the
common mode input voltage.
Inverting Gain and Transimpedance Gain
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the non-inverting
input pin (V
IN
+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., V
DD
/2 or ground).
b. Connect the inverting pin (V
IN
–) to the input
with a wire that does not touch the PCB
surface.
©
2005 Microchip Technology Inc.
DS21733F-page 9