MCP413X/415X/423X/425X
1.1
SPI Mode Timing Waveforms and Requirements
VIHH
VIH
VIH
84
CS
VIL
70
72
SCK
83
71
80
78
79
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
FIGURE 1-1:
SPI Timing Waveform (Mode = 11).
TABLE 1-1:
#
SPI REQUIREMENTS (MODE = 11)
Characteristic
Symbol
Min
Max Units
Conditions
SCK Input Frequency
FSCK
—
—
10
1
MHz VDD = 2.7V to 5.5V
MHz VDD = 1.8V to 2.7V
ns
70 CS Active (VIL or VIHH) to SCK↑ input
71 SCK input high time
TcsA2scH
TscH
60
45
500
45
500
10
20
—
—
—
—
—
—
—
—
50
70
170
—
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns
72 SCK input low time
TscL
73 Setup time of SDI input to SCK↑ edge
74 Hold time of SDI input from SCK↑ edge
77 CS Inactive (VIH) to SDO output hi-impedance
80 SDO data output valid after SCK↓ edge
TDIV2scH
TscH2DIL
TcsH2DOZ
TscL2DOV
ns
ns Note 1
—
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns VDD = 2.7V to 5.5V
ms VDD = 1.8V to 2.7V
ns
83 CS Inactive (VIH) after SCK↑ edge
TscH2csI
TcsA2csI
100
1
84 Hold time of CS Inactive (VIH) to
50
—
CS Active (VIL or VIHH
)
Note 1: This specification by design.
© 2008 Microchip Technology Inc.
DS22060B-page 11