MCP3204/3208
t
t
CYC
CYC
t
CSH
CS
t
SUCS
CLK
SGL/
DIFF
SGL/
DIFF
D
Don’t Care
Start
Start
D2 D1 D0
D2
IN
HI-Z
HI-Z
Null
Bit
D
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
OUT
t
CONV
t
t
**
SAMPLE
DATA
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB
first data, followed by zeros indefinitely (see Figure 5-2 below).
** tDATA: during this time, the bias current and the comparator power down while the reference input becomes
a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-1:
Communication with the MCP3204 or MCP3208.
t
CYC
t
CSH
CS
t
SUCS
Power Down
CLK
Start
D
Don’t Care
D2 D1 D0
IN
SGL/
DIFF
HI-Z
*
Null
Bit
HI-Z
B11
B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11
B10 B9
D
OUT
(MSB)
t
**
t
DATA
CONV
t
SAMPLE
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros
indefinitely.
** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a
high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
FIGURE 5-2:
Communication with MCP3204 or MCP3208 in LSB First Format.
DS21298D-page 16
© 2007 Microchip Technology Inc.
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