MCP3204/3208
This diagram illustrates that the source impedance (RS)
adds to the internal sampling switch (RSS) impedance,
directly effecting the time that is required to charge the
capacitor (Csample). Consequently, larger source
impedances increase the offset, gain and integral
linearity errors of the conversion (see Figure 4-2).
EQUATION
Digital Output Code =
4096 × VIN
--------------------------
VREF
VIN = analog input voltage
REF = reference voltage
V
4.2
Reference Input
When using an external voltage reference device, the
system designer should always refer to the manufac-
turer’s recommendations for circuit layout. Any instabil-
ity in the operation of the reference device will have a
direct effect on the operation of the A/D converter.
For each device in the family, the reference input
(VREF) determines the analog input voltage range. As
the reference input is reduced, the LSB size is reduced
accordingly. The theoretical digital output code pro-
duced by the A/D converter is a function of the analog
input signal and the reference input, as shown below.
VDD
Sampling
Switch
VT = 0.6V
RS = 1 kΩ
CHx
RSS
SS
CSAMPLE
= DAC capacitance
= 20 pF
CPIN
7 pF
ILEAKAGE
VA
VT = 0.6V
±1 nA
VSS
Legend
VA
Signal Source
Leakage Current At The Pin
Due To Various Junctions
=
I
=
leakage
SS
Source Impedance
Input Channel Pad
Input Pin Capacitance
Threshold Voltage
Sampling switch
R
=
=
=
=
=
=
=
ss
CHx
Sampling switch resistor
Sample/hold capacitance
R
s
C
C
pin
sample
V
t
FIGURE 4-1:
Analog Input Model.
2.5
2.0
1.5
1.0
0.5
VDD = 5 V
VDD = 2.7 V
0.0
100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2:
Maximum Clock Frequency
vs. Input resistance (RS) to maintain less than a
0.1 LSB deviation in INL from nominal
conditions.
DS21298D-page 14
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
