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MCP2515-I/ST 参数 Datasheet PDF下载

MCP2515-I/ST图片预览
型号: MCP2515-I/ST
PDF下载: 下载PDF文件 查看货源
内容描述: 独立CAN控制器,SPI ™接口 [Stand-Alone CAN Controller With SPI⑩ Interface]
分类和应用: 控制器
文件页数/大小: 84 页 / 993 K
品牌: MICROCHIP [ MICROCHIP ]
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MCP2515  
1.5.3  
ERROR MANAGEMENT LOGIC  
1.5  
CAN Protocol Engine  
The Error Management Logic (EML) is responsible for  
the fault confinement of the CAN device. Its two  
counters, the Receive Error Counter (REC) and the  
Transmit Error Counter (TEC), are incremented and  
decremented by commands from the bit stream  
processor. Based on the values of the error counters,  
the CAN controller is set into the states error-active,  
error-passive or bus-off.  
The CAN protocol engine combines several functional  
blocks, shown in Figure 1-4 and described below.  
1.5.1  
PROTOCOL FINITE STATE  
MACHINE  
The heart of the engine is the Finite State Machine  
(FSM). The FSM is a sequencer that controls the  
sequential data stream between the TX/RX shift  
register, the CRC register and the bus line. The FSM  
also controls the Error Management Logic (EML) and  
the parallel data stream between the TX/RX shift  
registers and the buffers. The FSM ensures that the  
processes of reception, arbitration, transmission and  
error-signaling are performed according to the CAN  
protocol. The automatic retransmission of messages  
on the bus line is also handled by the FSM.  
1.5.4  
BIT TIMING LOGIC  
The Bit Timing Logic (BTL) monitors the bus line input  
and handles the bus-related bit timing according to the  
CAN protocol. The BTL synchronizes on a recessive-  
to-dominant bus transition at Start-of-Frame (hard syn-  
chronization) and on any further recessive-to-dominant  
bus line transition if the CAN controller itself does not  
transmit a dominant bit (resynchronization). The BTL  
also provides programmable time segments to  
compensate for the propagation delay time, phase  
shifts and to define the position of the sample point  
within the bit time. The programming of the BTL  
depends on the baud rate and external physical delay  
times.  
1.5.2  
CYCLIC REDUNDANCY CHECK  
The Cyclic Redundancy Check register generates the  
Cyclic Redundancy Check (CRC) code, which is  
transmitted after either the Control Field (for messages  
with 0 data bytes) or the Data Field and is used to  
check the CRC field of incoming messages.  
FIGURE 1-4:  
CAN PROTOCOL ENGINE BLOCK DIAGRAM  
TX  
RX  
Bit Timing Logic  
SAM  
Transmit Logic  
REC  
Receive  
Sample<2:0>  
Error Counter  
TEC  
StuffReg<5:0>  
Transmit  
ErrPas  
Majority  
Decision  
Error Counter  
BusOff  
BusMon  
Comparator  
CRC<14:0>  
Comparator  
Protocol  
FSM  
SOF  
Shift<14:0>  
(Transmit<5:0>, Receive<7:0>)  
Receive<7:0>  
Transmit<7:0>  
RecData<7:0>  
TrmData<7:0>  
Rec/Trm Addr.  
Interface to Standard Buffer  
DS21801D-page 6  
Preliminary  
© 2005 Microchip Technology Inc.  
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