MCP2210
TABLE 3-1:
Byte Index
17
COMMAND STRUCTURE (CONTINUED)
Meaning
Other Chip Settings – Enable/Disable Wake-up, Interrupt Counting, SPI Bus Release Options
• Bit 7 – Don’t Care
• Bit 6 – Don’t Care
• Bit 5 – Don’t Care
• Bit 4 – Remote Wake-up Enabled/Disabled
-
0
– Remote Wake-up Disabled
-
1
– Remote Wake-up Enabled
• Bit 3 – Dedicated Function – Interrupt Pin mode
• Bit 2 – Dedicated Function – Interrupt Pin mode
• Bit 1 – Dedicated Function – Interrupt Pin mode
- b111
– Reserved
- b110
– Reserved
- b101
– Reserved
-
b100
– Count High Pulses
-
b011
– Count Low Pulses
-
b010
– Count Rising Edges
-
b001
– Count Falling Edges
-
b000
– No Interrupt Counting
• Bit 0 – SPI Bus Release Enable
-
0
= SPI Bus is Released Between Transfer
-
1
= SPI Bus is Not Released by the MCP2210 between transfers
NVRAM Chip Parameters Access Control
• 0x00 – Chip settings not protected
• 0x40 – Chip settings protected by password access
• 0x80 – Chip settings permanently locked
New Password Character 0 (Note
New Password Character 1 (Note
New Password Character 2 (Note
New Password Character 3 (Note
New Password Character 4 (Note
New Password Character 5 (Note
New Password Character 6 (Note
New Password Character 7 (Note
Reserved
(fill with 0x00)
18
19
20
21
22
23
24
25
26
27-63
Note 1:
When the password does not need to change, this field must be filled with 0 (it applies to (byte index 19 to 26).
3.1.1.1
TABLE 3-2:
Byte
Index
0
1
2-63
Responses
RESPONSE 1 STRUCTURE
Meaning
0x60 –
Set Chip NVRAM Parameters
– echos back the given command code
0xFB –
Blocked Access
– The provided password is not matching the one stored in the chip, or the
settings are permanently locked.
Don’t Care
2011 Microchip Technology Inc.
DS22288A-page 13
MICROCHIP [ MICROCHIP TECHNOLOGY ]
