KSZ8041NL/RNL
7.10 Reset Circuit
The reset circuit in Figure 7-11 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power
supply.
FIGURE 7-11:
RECOMMENDED RESET CIRCUIT
3.3V
D1: 1N4148
D1
R
10k
KSZ8041NL
RST#
C
10µF
Figure 7-12 shows a reset circuit recommended for applications where reset is driven by another device (for example,
the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2
is required if using different VDDIO voltage between the switch and CPU/FPGA. Diode D2 should be selected to provide
maximum 0.3V VF (Forward Voltage), for example, VISHAY BAT54, MSS1P2L. Alternatively, a level shifter device can
also be used. D2 is not required if PHY and CPU/FPGA use same VDDIO voltage.
FIGURE 7-12:
RECOMMENDED RESET CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET
OUTPUT
3.3V
R
10k
D1
KSZ8041NL
RST#
CPU/FPGA
RST_OUT_n
D2
C
10µF
D1, D2: 1N4148
DS00002245B-page 48
2017 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
