KSZ8041NL/RNL
7.9
Power-Up/Reset Timing
The KSZ8041NL/RNL reset timing requirement is summarized in Figure 7-10 and Figure 7-10.
FIGURE 7-10: POWER-UP/RESET TIMING
TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS
Parameters
Description
Min
Max
Units
Supply Voltage (VDDIO_3.3, VDDA_3.3) Rise
Time
tVR
250
—
µs
tsr
tcs
tch
trc
Stable Supply Voltage to Reset High
Configuration Setup Time
10
5
—
—
—
—
ms
ns
ns
ns
Configuration Hold Time
5
Reset to Strap-In Pin Output
6
The supply voltage (VDDIO_3.3 and VDDA_3.3) power-up waveform should be monotonic. The 250 µs minimum rise time
is from 10% to 90%.
After the deassertion of reset, it is recommended to wait a minimum of 100 µs before starting programming on the MIIM
(MDC/MDIO) Interface.
2017 Microchip Technology Inc.
DS00002245B-page 47
MICROCHIP [ MICROCHIP ]
