KSZ8041NL/RNL
TABLE 4-2:
Address
REGISTER DESCRIPTIONS (CONTINUED)
Name Description
Mode
(Note 4-1)
Default
Register 8h – Link Partner Next Page Ability
1 = Additional Next Page(s) will
follow
0 = Last page
8.15
Next Page
RO
RO
0
0
1 = Successful receipt of link
word
0 = No successful receipt of link
word
8.14
Acknowledge
1 = Message page
0 = Unformatted page
8.13
8.12
Message Page
Acknowledge2
RO
RO
0
0
1 = Able to act on the information
0 = Not able to act on the
information
1 = Previous value of transmitted
link code word equal to logic zero
0 = Previous value of transmitted
link code word equal to logic one
8.11
Toggle
RO
0
8.10:0
Message Field
—
RO
RO
000_0000_0000
0000_0000
Register 14h – MII Control
14.15:8
Reserved
—
1 = Restore received preamble to
MII output (random latency)
0 = Consume 1-byte preamble
before sending frame to MII
output for fixed latency
0 or
100BASE-TX Preamble
Restore
1 (if CONFIG[2:0] = 100)
See Table 2-2 and
Table 2-4 for details.
14.7
RW
RW
1 = Restore received preamble to
MII output
0 = Remove all 7-bytes of
preamble before sending frame
(starting with SFD) to MII output
10BASE-T Preamble
Restore
14.6
0
14.5:0
Reserved
—
RO
00_0001
000h
Register 15h – RXER Counter
15.15:0 RXER Counter
Register 1Bh – Interrupt Control/Status
Receive error counter for Symbol
Error frames
RO/SC
1 = Enable Jabber Interrupt
0 = Disable Jabber Interrupt
1b.15
Jabber Interrupt Enable
RW
RW
0
0
1 = Enable Receive Error
Interrupt
0 = Disable Receive Error
Interrupt
Receive Error Interrupt
Enable
1b.14
1 = Enable Page Received
Interrupt
0 = Disable Page Received
Interrupt
Page Received Interrupt
Enable
1b.13
1b.12
RW
RW
0
0
1 = Enable Parallel Detect Fault
Interrupt
0 = Disable Parallel Detect Fault
Interrupt
Parallel Detect Fault Inter-
rupt Enable
DS00002245B-page 34
2017 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
