KSZ8041NL/RNL
4.2
Register Descriptions
Table 4-2 provides a list of supported registers and their descriptions.
TABLE 4-2:
Address
REGISTER DESCRIPTIONS
Name
Mode
(Note 4-1)
Description
Default
Register 0h – Basic Control
1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’
is written to it.
0.15
0.14
Reset
RW/SC
RW
0
0
1 = Loop-back mode
0 = Normal operation
Loop-Back
1 = 100 Mbps
0 = 10 Mbps
This bit is ignored if auto-negotia-
tion is enabled (register 0.12 =
1).
Set by SPEED strapping
pin.
See Table 2-2 and
Table 2-4 for details.
0.13
0.12
Speed Select (LSB)
RW
RW
1 = Enable auto-negotiation
process
0 = Disable auto-negotiation
process
If enabled, auto-negotiation
result overrides the settings in
register 0.13 and 0.8.
Set by NWAYEN strap-
ping pin.
See Table 2-2 and
Table 2-4 for details.
Auto-Negotiation Enable
1 = Power-down mode
0 = Normal operation
0.11
0.10
Power Down
Isolate
RW
RW
0
1 = Electrical isolation of PHY
from MII and TX+/TX-
Set by ISO strapping pin.
See Table 2-2 and
0 = Normal operation
Table 2-4 for details.
1 = Restart auto-negotiation
process
0.9
0.8
Restart Auto-Negotiation
Duplex Mode
0 = Normal operation
This bit is self-cleared after a ‘1’
is written to it.
RW/SC
RW
0
Inverse of DUPLEX
strapping pin value.
See Table 2-2 and
Table 2-4 for details.
1 = Full-duplex
0 = Half-duplex
1 = Enable COL test
0 = Disable COL test
0.7
0.6:1
0.0
Collision Test
Reserved
RW
RO
RW
0
000_000
0
Disable
Transmitter
0 = Enable transmitter
1 = Disable transmitter
Register 1h – Basic Status
1 = T4 capable
0 = Not T4 capable
1.15
100BASE-T4
RO
RO
0
1
1 = Capable of 100 Mbps full-
duplex
0 = Not capable of 100 Mbps full-
duplex
1.14
100BASE-TX Full Duplex
DS00002245B-page 30
2017 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
