ENC28J60
FIGURE 16-1:
SPI INPUT TIMING
TCSS
TCSD
TCSH
CS
SCK
TSU THD
MSb In
LSb In
SI
1/FSCK
SO
High-Impedance
FIGURE 16-2:
SPI OUTPUT TIMING
CS
SCK
SO
TDIS
TV
TV
MSb Out
LSb Out
1/FSCK
LSb In
SI
Don’t Care
TABLE 16-6: SPI INTERFACE AC CHARACTERISTICS
Param.
Sym
Characteristic
Min
Max
Units
Conditions
No.
FSCK
Clock Frequency
DC
50
10
210
50
10
10
—
20
—
—
—
—
—
—
10
10
MHz
ns
1
2
TCSS
CS Setup Time
ns
ETH registers and memory buffer
MAC and MII registers
TCSH
CS Hold Time
ns
3
4
5
6
7
TCSD
TSU
THD
TV
CS Disable Time
ns
Data Setup Time
ns
Data Hold Time
ns
Output Valid from Clock Low
Output Disable Time
ns
SO Load = 30 pF
SO Load = 30 pF
TDIS
—
ns
DS39662B-page 82
Preliminary
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
