ENC28J60
REGISTER 6-2:
MACON3: MAC CONTROL REGISTER 3
R/W-0
R/W-0
PADCFG1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PADCFG2
bit 7
PADCFG0
TXCRCEN
PHDREN
HFRMEN
FRMLNEN
FULDPX
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
PADCFG2:PADCFG0: Automatic Pad and CRC Configuration bits
111= All short frames will be zero padded to 64 bytes and a valid CRC will then be appended
110= No automatic padding of short frames
101= MAC will automatically detect VLAN Protocol frames which have a 8100h type field and auto-
matically pad to 64 bytes. If the frame is not a VLAN frame, it will be padded to 60 bytes. After
padding, a valid CRC will be appended.
100= No automatic padding of short frames
011= All short frames will be zero padded to 64 bytes and a valid CRC will then be appended
010= No automatic padding of short frames
001= All short frames will be zero padded to 60 bytes and a valid CRC will then be appended
000= No automatic padding of short frames
bit 4
bit 3
TXCRCEN: Transmit CRC Enable bit
1= MAC will apend a valid CRC to all frames transmitted regardless of PADCFG. TXCRCEN must be
set if PADCFG specifies that a valid CRC will be appended.
0= MAC will not append a CRC. The last 4 bytes will be checked and if it is an invalid CRC, it will be
reported in the transmit status vector.
PHDREN: Proprietary Header Enable bit
1= Frames presented to the MAC contain a 4-byte proprietary header which will not be used when
calculating the CRC
0= No proprietary header is present. The CRC will cover all data (normal operation).
bit 2
bit 1
HFRMEN: Huge Frame Enable bit
1= Frames of any size will be allowed to be transmitted and receieved
0= Frames bigger than MAMXFL will be aborted when transmitted or received
FRMLNEN: Frame Length Checking Enable bit
1= The type/length field of transmitted and received frames will be checked. If it represents a length, the
frame size will be compared and mismatches will be reported in the transmit/receive status vector.
0= Frame lengths will not be compared with the type/length field
bit 0
FULDPX: MAC Full-Duplex Enable bit
1= MAC will operate in Full-Duplex mode. PDPXMD bit must also be set.
0= MAC will operate in Half-Duplex mode. PDPXMD bit must also be clear.
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 35
MICROCHIP [ MICROCHIP ]
