ENC28J60
10.0
FLOW CONTROL
The ENC28J60 implements hardware flow control for
both Full and Half-Duplex modes. The operation of this
feature differs depending on which mode is being used.
matically decrement every 512 bit times or 51.2
μs.
While the timer is counting down, reception of packets
is still enabled. If new pause frames arrive, the timer will
be reinitialized with the new pause timer value. When
the timer reaches zero or was sent a frame with a zero
pause timer value, the MAC that received the pause
frame will resume transmitting any pending packets. To
prevent a pause frame from stopping all traffic on the
entire network, Ethernet switches and routers do not
propagate pause control frames in Full-Duplex mode.
The pause operation only applies to the recipient.
A sample network is shown in Figure 10-1. If
Computer A were to be transmitting too much data to
the ENC28J60 in Full-Duplex mode, the ENC28J60
could transmit a pause control frame to stop the data
which is being sent to it. The Ethernet switch would
take the pause frame and stop sending data to the
ENC28J60. If Computer A continues to send data, the
Ethernet switch will buffer the data so it can be
transmitted later when its pause timer expires. If the
Ethernet switch begins to run out of buffer space, it will
likely transmit a pause control frame of its own to
Computer A. If, for some reason, the Ethernet switch
does not generate a pause control frame of its own, or
one of the nodes does not properly handle the pause
frame it receives, then packets will inevitably be
dropped. In any event, any communication between
Computer A and Computer B will always be completely
unaffected.
10.1
Half-Duplex Mode
In Half-Duplex mode, setting the EFLOCON.FCEN0 bit
causes flow control to be enabled. When FCEN0 is set,
a continuous preamble pattern of alternating ‘1’s and
‘0’s (55h) will automatically be transmitted on the
Ethernet medium. Any connected nodes will see the
transmission and either not transmit anything, waiting
for the ENC28J60’s transmission to end, or will attempt
to transmit and immediately cause a collision. Because
a collision will always occur, no nodes on the network
will be able to communicate with each other and no
new packets will arrive.
When the host controller tells the ENC28J60 to
transmit a packet by setting ECON1.TXRTS, the
preamble pattern will stop being transmitted. An Inter-
Packet Gap delay will pass as configured by register
MABBIPG and then the ENC28J60 will attempt to
transmit its packet. During the Inter-Packet Gap delay,
other nodes may begin to transmit. Because all traffic
was jammed previously, several nodes may begin
transmitting and a series of collisions may occur. When
the ENC28J60 successfully finishes transmitting its
packet or aborts it, the transmission of the preamble
pattern will automatically restart. When the host
controller wishes to no longer jam the network, it should
clear the FCEN0 bit. The preamble transmission will
cease and normal network operation will resume.
Given the detrimental network effects that are possible
and lack of effectiveness, it is not recommend that half-
duplex flow control be used unless the application will
be in a closed network environment with proper testing.
FIGURE 10-1:
SAMPLE FULL-DUPLEX
NETWORK
Computer A
Computer B
10.2
Full-Duplex Mode
In Full-Duplex mode (MACON3.FULDPX =
1),
hardware
flow control is implemented by means of transmitting
pause control frames as defined by the IEEE 802.3
specification. Pause control frames are 64-byte frames
consisting of the reserved multicast destination address
of 01-80-C2-00-00-01, the source address of the sender,
a special pause opcode, a two-byte pause timer value
and padding/CRC.
Normally, when a pause control frame is received by a
MAC, the MAC will finish the packet it is transmitting
and then stop transmitting any new frames. The pause
timer value will be extracted from the control frame and
used to initialize an internal timer. The timer will auto-
Ethernet Switch
MCP22S80
E N C 28 J 6 0
©
2006 Microchip Technology Inc.
Preliminary
DS39662B-page 55
MICROCHIP [ MICROCHIP TECHNOLOGY ]
