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ENC28J60-I/ML 参数 Datasheet PDF下载

ENC28J60-I/ML图片预览
型号: ENC28J60-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 独立以太网控制器,SPI接口 [Stand-Alone Ethernet Controller with SPI Interface]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输PC局域网以太网时钟
文件页数/大小: 96 页 / 1466 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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ENC28J60
9.0
DUPLEX MODE
CONFIGURATION AND
NEGOTIATION
2.
If the collision occurs after the number of bytes
specified by the “Collision Window” in
MACLCON2 were transmitted, the packet will be
immediately aborted without any retransmission
attempts. Ordinarily, in 802.3 compliant
networks which are properly configured, this late
collision will not occur. User intervention may be
required to correct the issue. This problem may
occur as a result of a full-duplex node attempting
to transmit on the half-duplex medium. Alter-
nately, the ENC28J60 may be attempting to
operate in Half-Duplex mode while it may be
connected to a full-duplex network. Excessively
long cabling and network size may also be a
possible cause of late collisions.
The ENC28J60 does not support automatic duplex
negotiation. If it is connected to an automatic duplex
negotiation enabled network switch or Ethernet control-
ler, the ENC28J60 will be detected as a half-duplex
device. To communicate in Full-Duplex mode, the
ENC28J60 and the remote node (switch, router or
Ethernet controller) must be manually configured for
full-duplex operation.
9.1
Half-Duplex Operation
The ENC28J60 operates in Half-Duplex mode when
MACON3.FULDPX =
0
and PHCON1.PDPXMD =
0.
If
only one of these two bits is set, the ENC28J60 will be
in an indeterminate state and not function correctly.
Since switching between Full and Half-Duplex modes
may result in this indeterminate state, the host control-
ler should not transmit any packets (maintain
ECON1.TXRTS clear) and packet reception should be
disabled (ECON1.RXEN and ESTAT.RXBUSY should
be clear) during this period.
In Half-Duplex mode, only one Ethernet controller may
be transmitting on the physical medium at any time. If
the host controller sets the ECON1.TXRTS bit,
requesting that a packet be transmitted while another
Ethernet controller is already transmitting, the
ENC28J60 will delay, waiting for the remote transmitter
to stop. After the transmission stops, the ENC28J60
will attempt to transmit its packet. If another Ethernet
controller starts transmitting at approximately the same
time that the ENC28J60 starts transmitting, the data on
the wire will become corrupt and a collision will occur.
The hardware will handle this condition in one of two
ways:
1.
If the collision occurs before the number of bytes
specified by the “Collision Window” in
MACLCON2
were
transmitted,
the
ECON1.TXRTS bit will remain set, a random
exponential back off delay will elapse as defined
by the IEEE 802.3 specification and then a new
attempt to transmit the packet from the begin-
ning will occur. The host controller will not need
to intervene. If the number of retransmission
attempts already matches the “Retransmission
Maximum” (RETMAX) defined in MACLCON1,
the packet will be aborted and ECON1.TXRTS
will be cleared. The host controller will then be
responsible for taking appropriate action. The
host controller will be able to determine that the
packet was aborted instead of being success-
fully transmitted by reading the ESTAT.TXABRT
flag. For more information, see
A transmit abort will
cause the transmit error interrupt.
When set in Half-Duplex mode, the Reset default
configuration will loop transmitted packets back to
itself. Unless the receive filter configuration filters these
packets out, they will be written into the circular receive
buffer, just as any other network traffic. To stop this
behavior, the host controller should set the
PHCON2.HDLDIS bit.
9.2
Full-Duplex Operation
The ENC28J60 operates in Full-Duplex mode when
MACON3.FULDPX =
1
and PHCON1.PDPXMD =
1.
If
only one of these two bits is clear, the ENC28J60 will
be in an indeterminate state and not function correctly.
Since switching between Full and Half-Duplex modes
may result in this indeterminate state, the host control-
ler should not transmit any packets (maintain
ECON1.TXRTS clear) and packet reception should be
disabled (ECON1.RXEN and ESTAT.RXBUSY should
be clear) during this period.
In Full-Duplex mode, packets will be transmitted
simultaneously while packets may be received. Given
this, it is impossible to cause any collisions when trans-
mitting packets. Several configuration fields, such as
“Retransmission Maximum” (RETMAX) in MACLCON1
and “Collision Window” (COLWIN) in MACLCON2, will
not be used.
When set in Full-Duplex mode, the Reset default
configuration will not loop transmitted packets back to
itself. If loopback is desired for diagnostic purposes, the
PHCON1.PLOOPBK bit should be set by the host
controller. Enabling loopback in Full-Duplex mode will
disable the twisted pair output driver and ignore all
incoming data, thus dropping any link (if established).
All packets received as a result of the loopback config-
uration will be subject to all enabled receive filters, just
as ordinary network traffic would be.
©
2006 Microchip Technology Inc.
Preliminary
DS39662B-page 53