欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA48V-10MUR 参数 Datasheet PDF下载

ATMEGA48V-10MUR图片预览
型号: ATMEGA48V-10MUR
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 4KB FLASH 32VQFN]
分类和应用: 时钟微控制器外围集成电路闪存
文件页数/大小: 359 页 / 2546 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第60页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第61页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第62页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第63页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第65页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第66页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第67页浏览型号ATMEGA48V-10MUR的Datasheet PDF文件第68页  
10. I/O-Ports  
10.1 Introduction  
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.  
This means that the direction of one port pin can be changed without unintentionally changing  
the direction of any other pin with the SBI and CBI instructions. The same applies when chang-  
ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as  
input). Each output buffer has symmetrical drive characteristics with both high sink and source  
capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-  
vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have  
protection diodes to both VCC and Ground as indicated in Figure 10-1. Refer to ”Electrical Char-  
acteristics” on page 299 for a complete list of parameters.  
Figure 10-1. I/O Pin Equivalent Schematic  
Rpu  
Pxn  
Logic  
Cpin  
See Figure  
"General Digital I/O" for  
Details  
All registers and bit references in this section are written in general form. A lower case “x” repre-  
sents the numbering letter for the port, and a lower case “n” represents the bit number. However,  
when using the register or bit defines in a program, the precise form must be used. For example,  
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-  
ters and bit locations are listed in ”Register Description for I/O Ports” on page 81.  
Three I/O memory address locations are allocated for each port, one each for the Data Register  
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins  
I/O location is read only, while the Data Register and the Data Direction Register are read/write.  
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-  
ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the  
pull-up function for all pins in all ports when set.  
Using the I/O port as General Digital I/O is described in ”Ports as General Digital I/O” on page  
65. Most port pins are multiplexed with alternate functions for the peripheral features on the  
device. How each alternate function interferes with the port pin is described in ”Alternate Port  
Functions” on page 69. Refer to the individual module sections for a full description of the alter-  
nate functions.  
64  
ATmega48/88/168  
2545E–AVR–02/05  
 
 
 复制成功!