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ATMEGA48V-10MUR 参数 Datasheet PDF下载

ATMEGA48V-10MUR图片预览
型号: ATMEGA48V-10MUR
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 4KB FLASH 32VQFN]
分类和应用: 时钟微控制器外围集成电路闪存
文件页数/大小: 359 页 / 2546 K
品牌: MICROCHIP [ MICROCHIP ]
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ATmega48/88/168  
If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from  
either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding  
Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in  
SREG is set.  
If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save  
mode.  
The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save  
mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is  
stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is  
stopped during sleep. Note that even if the synchronous clock is running in Power-save, this  
clock is only available for Timer/Counter2.  
7.5  
Standby Mode  
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the  
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down  
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up  
in six clock cycles.  
Table 7-2.  
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.  
Active Clock Domains Oscillators Wake-up Sources  
Sleep Mode  
Idle  
X
X
X
X
X
X
X
X(2)  
X(2)  
X
X
X
X
X
X
X
X
X
X
X
X
ADC Noise  
Reduction  
X(3)  
Power-down  
Power-save  
Standby(1)  
X(3)  
X(3)  
X(3)  
X
X
X
X
X
X
X
X
X
X
Notes: 1. Only recommended with external crystal or resonator selected as clock source.  
2. If Timer/Counter2 is running in asynchronous mode.  
3. For INT1 and INT0, only level interrupt.  
7.6  
Power Reduction Register  
The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher-  
als to reduce power consumption. The current state of the peripheral is frozen and the I/O  
registers can not be read or written. Resources used by the peripheral when stopping the clock  
will remain occupied, hence the peripheral should in most cases be disabled before stopping the  
clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the  
same state as before shutdown.  
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall  
power consumption. See ”Power-Down Supply Current” on page 315 for examples. In all other  
sleep modes, the clock is already stopped.  
39  
2545E–AVR–02/05  
 
 
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