26.10 Parallel Programming Characteristics
Figure 26-5. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
XTAL1
tXHXL
tDVXH
tXLDX
Data and Control
(DATA, XA0/1, BS1, BS2)
tBVPH
tPLBX
tBVWL
tWLBX
PAGEL
WR
tPHPL
tWLWH
tPLWL
tWLRL
RDY/BSY
tWLRH
Figure 26-6. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
Load Address
(Low Byte)
Load Data
(Low Byte)
Load Data
(High Byte)
Load Address
(Low Byte)
Load Data
tXLPH
tXLXH
tPLXH
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 25-7 on page 268 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading
operation.
282
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
