26.7 SPI Timing Characteristics
See Figure 26-3 and Figure 26-4 on page 279 for details.
Table 26-4. SPI Timing Parameters
No.
1
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Mode
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Min.
Typ.
Max.
Unit
See Table 15-4 on page 139
2
50% duty cycle
3
3.6
10
4
5
Hold
10
6
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low (1)
Rise/Fall time
Setup
0.5 tsck
10
7
8
10
9
15
ns
10
11
12
13
14
15
16
17
Slave
4 tck
2 tck
Slave
1600
Slave
Slave
10
tck
Hold
Slave
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
Slave
15
10
20
Slave
Slave
18
Slave
20
Note:
In SPI Programming mode the minimum SCK high/low period is:
–2 tCLCL for fCK < 12MHz
–3 tCLCL for fCK >12MHz
Figure 26-3. SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
4
5
3
MISO
MSB
...
...
LSB
(Data Input)
8
7
MOSI
(Data Output)
MSB
LSB
278
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
