Figure 25-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)
Load Address
(Low Byte)
Read Data
(Low Byte)
Read Data
(High Byte)
Load Address
(Low Byte)
tXLOL
XTAL1
BS1
tBVDV
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 25-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
Table 25-15. Parallel Programming Characteristics, VCC = 5V ±10%
Parameter
Symbol
Min
Typ
Max
12.5
250
Unit
V
Programming enable voltage
Programming enable current
Data and control valid before XTAL1 high
XTAL1 low to XTAL1 high
XTAL1 pulse width high
VPP
IPP
11.5
A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ms
ms
ns
ns
ns
ns
tDVXH
tXLXH
tXHXL
tXLDX
tXLWL
tXLPH
tPLXH
tBVPH
tPHPL
tPLBX
tWLBX
tPLWL
tBVWL
tWLWH
tWLRL
tWLRH
tWLRH_CE
tXLOL
tBVDV
tOLDV
tOHDZ
67
200
150
67
0
Data and control hold after XTAL1 low
XTAL1 low to WR low
XTAL1 low to PAGEL high
PAGEL low to XTAL1 high
BS1 valid before PAGEL high
PAGEL pulse width high
BS1 hold after PAGEL low
BS2/1 hold after WR low
PAGEL low to WR low
0
150
67
150
67
67
67
67
150
0
BS1 valid to WR low
WR pulse width low
WR low to RDY/BSY low
WR low to RDY/BSY high(1)
WR low to RDY/BSY high for chip erase(2)
XTAL1 low to OE low
1
4.5
9
3.7
7.5
0
BS1 valid to DATA valid
0
250
250
250
OE low to DATA valid
OE high to DATA tri-stated
Notes: 1. tWLRH is valid for the write flash, write EEPROM, write fuse bits and write lock bits commands.
2. WLRH_CE is valid for the chip erase command.
t
ATmega16/32/64/M1/C1 [DATASHEET]
269
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
