AT24C256C
Device Operation and Communication
5.5
Software Reset
After an interruption in protocol, power loss or system Reset, any 2‑wire device can be protocol reset by
clocking SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDA
is released by the EEPROM will vary. The software Reset sequence should not take more than nine
dummy clock cycles. Once the software Reset sequence is complete, new protocol can be sent to the
device by sending a Start condition followed by the protocol. Refer to Figure 5-2 for an illustration.
Figure 5-2.ꢀSoftware Reset
Dummy Clock Cycles
SCL
1
2
3
8
9
SDA Released
by EEPROM
Device is
Software Reset
SDA
In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must
be used to reset the device (see 4.5.1 Power-up Requirements and Reset Behavior).
DS20006042A-page 15
Datasheet
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