93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (T
CSL
).
Note:
Issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
V
CC
must be
≥
4.5V for proper operation of ERAL.
FIGURE 2-3:
CS
ERAL TIMING FOR 93AA AND 93LC DEVICES
T
CSL
Check Status
CLK
DI
1
0
0
1
0
x
•••
x
T
SV
T
CZ
Ready
High-Z
T
EC
DO
High-Z
Busy
V
CC
must be
≥
4.5V for proper operation of ERAL.
FIGURE 2-4:
CS
ERAL TIMING FOR 93C DEVICES
T
CSL
Check Status
CLK
DI
1
0
0
1
0
x
•••
x
T
SV
T
CZ
Ready
High-Z
T
EC
DO
High-Z
Busy
DS21795C-page 8
©
2005 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
