93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
FIGURE 1-1:
CS
V
IH
V
IL
V
IH
CLK
V
IL
T
DIS
V
IH
DI
V
IL
T
PD
DO
(Read)
DO
(Program)
V
OH
V
OL
V
OH
Status Valid
V
OL
T
SV
is relative to CS.
T
CZ
T
SV
T
PD
T
CZ
T
DIH
T
CSS
T
CKH
T
CKL
T
CSH
SYNCHRONOUS DATA TIMING
Note:
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX66B OR 93XX66C WITH ORG =
1)
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
SB
1
1
1
1
1
1
1
Opcode
11
00
00
00
10
01
00
Address
A7 A6 A5 A4 A3 A2 A1 A0
1
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Data In
—
—
—
—
—
D15 – D0
D15 – D0
Data Out
(RDY/BSY)
(RDY/BSY)
High-Z
High-Z
D15 – D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
11
11
11
11
27
27
27
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
0
1
X
X
X
X
X
X
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX66A OR 93XX66C WITH ORG =
0)
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
SB
1
1
1
1
1
1
1
Opcode
11
00
00
00
10
01
00
Address
A8 A7 A6 A5 A4 A3 A2 A1 A0
1
0
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Data In
—
—
—
—
—
D7 – D0
D7 – D0
Data Out
(RDY/BSY)
(RDY/BSY)
High-Z
High-Z
D7 – D0
(RDY/BSY)
(RDY/BSY)
Req. CLK
Cycles
12
12
12
12
20
20
20
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
X
X
X
X
X
X
X
©
2005 Microchip Technology Inc.
DS21795C-page 5
MICROCHIP [ MICROCHIP TECHNOLOGY ]
