93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
FIGURE 1-1:
CS
V
IH
V
IL
V
IH
CLK
V
IL
T
DIS
V
IH
DI
V
IL
T
PD
DO
(READ)
V
OH
V
OL
T
CZ
T
SV
STATUS VALID
T
PD
T
CZ
T
DIH
T
CSS
T
CKH
T
CKL
T
CSH
SYNCHRONOUS DATA TIMING
DO V
OH
(PROGRAM)
V
OL
Note:
T
SV
is relative to CS.
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
SB
1
1
1
1
1
1
1
Opcode
11
00
00
00
10
01
00
A5
1
0
1
A5
A5
0
A4
0
0
1
A4
A4
1
Address
A3
X
X
X
A3
A3
X
A2
X
X
X
A2
A2
X
A1
X
X
X
A1
A1
X
A0
X
X
X
A0
A0
X
Data In
—
—
—
—
—
D15 - D0
D15 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
9
9
9
9
25
25
25
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
SB
1
1
1
1
1
1
1
Opcode
11
00
00
00
10
01
00
A6
1
0
1
A6
A6
0
A5
0
0
1
A5
A5
1
Address
A4
X
X
X
A4
A4
X
A3
X
X
X
A3
A3
X
A2
X
X
X
A2
A2
X
A1
X
X
X
A1
A1
X
A0
X
X
X
A0
A0
X
Data In
—
—
—
—
—
D7 - D0
D7 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
10
10
10
10
18
18
18
DS21749D-page 4
2003 Microchip Technology Inc.