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24LC65-I/SM 参数 Datasheet PDF下载

24LC65-I/SM图片预览
型号: 24LC65-I/SM
PDF下载: 下载PDF文件 查看货源
内容描述: 64K 1.8V I2C串行智能Ø EEPROM [64K 1.8V I2C Smart Serial O EEPROM]
分类和应用: 存储内存集成电路光电二极管PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 24 页 / 285 K
品牌: MICROCHIP [ MICROCHIP ]
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24AA65/24LC65/24C65  
TABLE 1-2:  
AC CHARACTERISTICS  
VCC = 1.8V-6.0V VCC = 4.5-6.0V  
STD. Mode FAST Mode  
Parameter  
Symbol  
Units  
Remarks  
Min  
Max  
Min  
Max  
Clock frequency  
FCLK  
THIGH  
TLOW  
TR  
4000  
4700  
100  
600  
1300  
400  
kHz  
ns  
Clock high time  
Clock low time  
ns  
SDA and SCL rise time  
SDA and SCL fall time  
Start condition setup time  
1000  
300  
300  
300  
ns  
(Note 1)  
TF  
ns  
(Note 1)  
THD:STA 4000  
600  
ns  
After this period the first  
clock pulse is generated  
Start condition setup time  
TSU:STA  
4700  
600  
ns  
Only relevant for  
repeated Start condition  
Data input hold time  
Data input setup time  
Stop condition setup time  
Output valid from clock  
Bus free time  
THD:DAT  
TSU:DAT  
TSU:STO  
TAA  
0
0
ns  
ns  
ns  
ns  
ns  
250  
4000  
100  
600  
3500  
900  
(Note 2)  
TBUF  
4700  
1300  
Time the bus must be  
free before a new  
transmission can start  
Output fall time from VIH min to TOF  
VIL max  
50  
250  
5
20 + 0.1  
CB  
250  
5
ns  
ns  
(Note 1), CB 100 pF  
Input filter spike suppression  
(SDA and SCL pins)  
TSP  
50  
(Note 3)  
Write cycle time  
TWR  
ms/page (Note 4)  
Endurance  
High Endurance Block  
Rest of Array  
10M  
1M  
10M  
1M  
cycles 25°C, (Note 5)  
Note 1: Not 100 percent tested. CB = total capacitance of one bus line in pF.  
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region  
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.  
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved  
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.  
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write  
cache for total time.  
5: This parameter is not tested but ensured by characterization. For endurance estimates in a specific  
application, please consult the Total Endurance™ Model which can be downloaded at www.microchip.com.  
FIGURE 1-2:  
BUS TIMING DATA  
TF  
TR  
THIGH  
TLOW  
THD:STA  
SCL  
TSU:STA  
THD:DAT  
TSU:DAT  
TSU:STO  
SDA  
IN  
TSP  
TBUF  
TAA  
TAA  
SDA  
OUT  
DS21073J-page 4  
2003 Microchip Technology Inc.  
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