24LC21A
FIGURE 3-5:
BUS TIMING START/STOP
SCL
T
HD
:
STA
T
SU
:
STA
SDA
V
HYS
T
SU
:
STO
Start
Stop
FIGURE 3-6:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
SP
T
AA
SDA
OUT
T
AA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
3.1.6
SLAVE ADDRESS
FIGURE 3-7:
After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LC21A.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LC21A
The 24LC21A monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
Operation
Read
Write
Slave Address
1010000
1010000
R/W
1
0
CONTROL BYTE
ALLOCATION
Read/Write
Start
Slave Address
R/W
A
1
0
1
0
0
0
0
DS21160G-page 8
©
2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
