24AA128/24LC128/24FC128
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
PIN FUNCTION TABLE
PDIP
SOIC
TSSOP MSOP
DFN(1)
TDFN(1)
CS
Function
A0
1
2
1
2
1
2
—
—
1, 2
3
1
2
1
2
3
2
User Configurable Chip Select
User Configurable Chip Select
Not Connected
A1
(NC)
A2
—
3
—
3
—
3
—
3
—
3
—
5
User Configurable Chip Select
Ground
VSS
SDA
SCL
WP
VCC
4
4
4
4
4
4
8
5
5
5
5
5
5
6
Serial Data
6
6
6
6
6
6
7
Serial Clock
7
7
7
7
7
7
4
Write-Protect Input
8
8
8
8
8
8
1
+1.7V to 5.5V (24AA128)
+2.5V to 5.5V (24LC128)
+1.7V to 5.5V (24FC128)
Note 1: The exposed pad on the DFN/TDFN package can be connected to VSS or left floating.
2.1
A0, A1, A2 Chip Address Inputs
2.3
Serial Clock (SCL)
The A0, A1 and A2 inputs are used by the 24XX128 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
This input is used to synchronize the data transfer to
and from the device.
2.4
Write-Protect (WP)
For the MSOP package only, pins A0 and A1 are not
connected.
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
3.0
FUNCTIONAL DESCRIPTION
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
The 24XX128 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions while the
24XX128 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2010 Microchip Technology Inc.
DS21191S-page 5
MICROCHIP [ MICROCHIP ]
