欢迎访问ic37.com |
会员登录 免费注册
发布采购

24LC128-I/P 参数 Datasheet PDF下载

24LC128-I/P图片预览
型号: 24LC128-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 128K I2C CMOS串行EEPROM [128K I2C CMOS Serial EEPROM]
分类和应用: 存储内存集成电路光电二极管双倍数据速率PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 26 页 / 427 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
 浏览型号24LC128-I/P的Datasheet PDF文件第1页浏览型号24LC128-I/P的Datasheet PDF文件第2页浏览型号24LC128-I/P的Datasheet PDF文件第4页浏览型号24LC128-I/P的Datasheet PDF文件第5页浏览型号24LC128-I/P的Datasheet PDF文件第6页浏览型号24LC128-I/P的Datasheet PDF文件第7页浏览型号24LC128-I/P的Datasheet PDF文件第8页浏览型号24LC128-I/P的Datasheet PDF文件第9页  
24AA128/24LC128/24FC128
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V T
A
= -40°C to +85°C
Automotive (E): V
CC
= +2.5V to 5.5V T
A
= -40°C to 125°C
Characteristic
Clock frequency
Min.
4000
600
600
500
4700
1300
1300
500
4000
600
600
250
4700
600
600
250
0
250
100
100
4000
600
600
250
4000
600
600
4700
1300
1300
Max.
100
400
400
1000
1000
300
300
300
100
Units
kHz
Conditions
1.7V
V
CC
<
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
<
2.5V 24FC128
2.5V
V
CC
5.5V 24FC128
1.7V
V
CC
<
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
<
2.5V 24FC128
2.5V
V
CC
5.5V 24FC128
1.7V
V
CC
<
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
<
2.5V 24FC128
2.5V
V
CC
5.5V 24FC128
1.7V
V
CC
<
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC128
All except, 24FC128
1.7V
V
CC
5.5V 24FC128
1.7V
V
CC
<
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
<
2.5V 24FC128
2.5V
V
CC
5.5V 24FC128
1.7V
V
CC
<
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
<
2.5V 24FC128
2.5V
V
CC
5.5V 24FC128
1.7V
V
CC
<
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC128
1.7 V
V
CC
<
2.5V
2.5 V
V
CC
5.5V
1.7V
V
CC
<
2.5V 24FC128
2.5 V
V
CC
5.5V 24FC128
1.7V
V
CC
<
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC128
1.7V
V
CC
<
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC128
AC CHARACTERISTICS
Param.
No.
1
Sym.
F
CLK
2
T
HIGH
Clock high time
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
SDA and SCL fall time
ns
5
6
T
F
ns
ns
T
HD
:
STA
Start condition hold time
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
ns
ns
10
T
SU
:
STO
Stop condition setup time
ns
11
T
SU
:
WP
WP setup time
ns
12
T
HD
:
WP
WP hold time
ns
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
©
2007 Microchip Technology Inc.
DS21191P-page 3