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24LC00T-I/SN 参数 Datasheet PDF下载

24LC00T-I/SN图片预览
型号: 24LC00T-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 128位I2C总线串行EEPROM [128 Bit I2C Bus Serial EEPROM]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 24 页 / 364 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
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24AA00/24LC00/24C00
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
Automotive (E):
Symbol
F
CLK
Min
4000
4000
600
4700
4700
1300
4000
4000
600
4700
4700
600
0
250
250
100
4000
4000
600
4700
4700
1300
20+0.1
CB
1M
T
A
= -40°C to +85°C, V
CC
= 1.8V to 5.5V
T
A
= -40°C to +125°C, V
CC
= 4.5V to 5.5V
Max
100
100
400
1000
1000
300
300
3500
3500
900
250
50
4
Units
kHz
Conditions
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
1.7V
Vcc
4.5V
4.5V
Vcc
5.5V
CB
100 pF
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Parameter
Clock frequency
Clock high time
T
HIGH
ns
Clock low time
T
LOW
ns
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
T
R
ns
T
F
T
HD
:
STA
ns
ns
Start condition setup time
T
SU
:
STA
ns
Data input hold time
Data input setup time
T
HD
:
DAT
T
SU
:
DAT
ns
ns
Stop condition setup time
T
SU
:
STO
ns
Output valid from clock
T
AA
ns
Bus free time: Time the bus must T
BUF
be free before a new transmis-
sion can start
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
Note 1:
2:
3:
4:
T
OF
T
SP
T
WC
ns
ns
ns
ms
cycles
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.
©
2007 Microchip Technology Inc.
DS21178G-page 3