24C01A/02A/04A
TABLE 1-3:
AC CHARACTERISTICS
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:S
TA
T
SU
:S
TA
T
HD
:D
AT
T
SU
:D
AT
T
AA
T
SU
:S
TO
T
BUF
Min.
—
4000
4700
—
—
4000
4700
0
250
300
4700
4700
Typ
—
—
—
—
—
—
—
—
—
—
—
—
Max.
100
—
—
1000
300
—
—
—
—
3500
—
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Time the bus must be free
before a new transmission
can start
Remarks
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
START condition setup time
Data input hold time
Data input setup time
Data output delay time
STOP condition setup time
Bus free time
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
Input filter time constant
(SDA and SCL pins)
Program cycle time
T
I
T
WC
—
—
—
.4
.4N
—
100
1
N
—
ns
ms
ms
cycles
Byte mode
Page mode, N=# of bytes
Endurance
—
1M
25
°
C, Vcc = 5.0V, Block
Mode (Note 2)
Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
HD
:
DAT
T
SP
T
AA
T
SU
:
DAT
T
SU
:
STO
T
AA
SDA
OUT
T
HD
:
STA
T
BUF
©
1996 Microchip Technology Inc.
DS11183D-page 3
MICROCHIP [ MICROCHIP TECHNOLOGY ]
