PIC16F818/819
TABLE 5-3:
Name
PORTB FUNCTIONS
Bit# Buffer
Function
RB0/INT
bit 0 TTL/ST(1) Input/output pin or external interrupt input.
Internal software programmable weak pull-up.
RB1/SDI/SDA
RB2/SDO/CCP1
bit 1 TTL/ST(5) Input/output pin, SPI™ data input pin or I2C™ data I/O pin.
Internal software programmable weak pull-up.
bit 2 TTL/ST(4) Input/output pin, SPI data output pin or
Capture input/Compare output/PWM output pin.
Internal software programmable weak pull-up.
RB3/CCP1/PGM(3)
bit 3 TTL/ST(2) Input/output pin, Capture input/Compare output/PWM output pin
or programming in LVP mode. Internal software programmable
weak pull-up.
RB4/SCK/SCL
RB5/SS
bit 4 TTL/ST(5) Input/output pin or SPI and I2C clock pin (with interrupt-on-change).
Internal software programmable weak pull-up.
bit 5
TTL
Input/output pin or SPI slave select pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB6/T1OSO/T1CKI/
PGC
bit 6 TTL/ST(2) Input/output pin, Timer1 oscillator output pin, Timer1 clock input pin or
serial programming clock (with interrupt-on-change).
Internal software programmable weak pull-up.
RB7/T1OSI/PGD
bit 7 TTL/ST(2) Input/output pin, Timer1 oscillator input pin or serial programming data
(with interrupt-on-change).
Internal software programmable weak pull-up.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: Low-Voltage ICSP™ Programming (LVP) is enabled by default which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 18-pin
mid-range devices.
4: This buffer is a Schmitt Trigger input when configured for CCP or SSP mode.
5: This buffer is a Schmitt Trigger input when configured for SPI or I2C mode.
TABLE 5-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
06h, 106h PORTB
86h, 186h TRISB
RB7
RB6
RB5
RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
1111 1111 1111 1111
PORTB Data Direction Register
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS39598E-page 44
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
