PIC16F818/819
FIGURE 5-5:
BLOCK DIAGRAM OF RA5/MCLR/VPP PIN
MCLRE
Schmitt Trigger
Buffer
MCLR Circuit
MCLR Filter
Data
Bus
RA5/MCLR/VPP
VSS
VSS
Schmitt Trigger
Input Buffer
RD TRIS
Q
D
EN
MCLRE
RD Port
FIGURE 5-6:
BLOCK DIAGRAM OF RA6/OSC2/CLKO PIN
From OSC1
Oscillator
Circuit
CLKO (FOSC/4)
VDD
P
VDD
RA6/OSC2/CLKO
VSS
(FOSC = 1x1)
N
Data
Bus
D
Q
Q
VSS
VDD
P
WR
PORTA
CK
Data Latch
D
Q
WR
TRISA
N
CK
Q
(FOSC = 1x0,011)
TRIS Latch
VSS
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
(FOSC = 1x0,011)
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
2: CLKO signal is 1/4 of the FOSC frequency.
2004 Microchip Technology Inc.
DS39598E-page 41