欢迎访问ic37.com |
会员登录 免费注册
发布采购

11AA02E64T-I/TT 参数 Datasheet PDF下载

11AA02E64T-I/TT图片预览
型号: 11AA02E64T-I/TT
PDF下载: 下载PDF文件 查看货源
内容描述: [SPI BUS SERIAL EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件页数/大小: 32 页 / 482 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号11AA02E64T-I/TT的Datasheet PDF文件第8页浏览型号11AA02E64T-I/TT的Datasheet PDF文件第9页浏览型号11AA02E64T-I/TT的Datasheet PDF文件第10页浏览型号11AA02E64T-I/TT的Datasheet PDF文件第11页浏览型号11AA02E64T-I/TT的Datasheet PDF文件第13页浏览型号11AA02E64T-I/TT的Datasheet PDF文件第14页浏览型号11AA02E64T-I/TT的Datasheet PDF文件第15页浏览型号11AA02E64T-I/TT的Datasheet PDF文件第16页  
11AA02E48/11AA02E64  
The following is a list of conditions under which the  
write enable latch will be reset:  
4.4  
Write Enable (WREN) and Write  
Disable (WRDI) Instructions  
• Power-up  
The 11AA02EXX contains a write enable latch. See  
Table 6-1 for the Write-Protect Functionality Matrix.  
This latch must be set before any write operation will be  
completed internally. The WRENinstruction will set the  
latch, and the WRDIinstruction will reset the latch.  
WRDIinstruction successfully executed  
WRSRinstruction successfully executed  
WRITEinstruction successfully executed  
ERALinstruction successfully executed  
SETALinstruction successfully executed  
Note:  
The WRENand WRDIinstructions must be  
terminated with a NoMAK following the  
command byte. If a NoMAK is not  
received at this point, the command will be  
considered invalid, and the device will go  
into Idle mode without responding with a  
SAK or executing the command.  
FIGURE 4-4:  
WRITE ENABLE COMMAND SEQUENCE  
Device Address  
Standby Pulse  
Start Header  
SCIO  
0 1 0 1 0 1 0 1  
1 0 1 0 0 0 0 0  
Command  
SCIO  
1 0 0 1 0 1 1 0  
FIGURE 4-5:  
WRITE DISABLE COMMAND SEQUENCE  
Device Address  
Standby Pulse  
Start Header  
SCIO  
SCIO  
0 1 0 1 0 1 0 1  
1 0 1 0 0 0 0 0  
Command  
1 0 0 1 0 0 0 1  
DS20002122D-page 12  
2008-2016 Microchip Technology Inc.