11AA02E48/11AA02E64
5.0
DATA PROTECTION
6.0
POWER-ON STATE
The following protection has been implemented to
prevent inadvertent writes to the array:
The 11AA02EXX powers on in the following state:
• The device is in low-power Shutdown mode,
requiring a low-to-high transition on SCIO to enter
Idle mode
• The Write Enable Latch (WEL) is reset on
power-up
• A Write Enable (WREN) instruction must be issued
to set the write enable latch
• The Write Enable Latch (WEL) is reset
• The internal Address Pointer is undefined
• After a write, ERAL, SETAL, or WRSR command,
the write enable latch is reset
• A low-to-high transition, standby pulse and
subsequent high-to-low transition on SCIO (the
first low pulse of the header) are required to enter
• Commands to access the array or write to the
status register are ignored during an internal write
cycle and programming is not affected
the active state
.
TABLE 6-1:
WEL
WRITE PROTECT FUNCTIONALITY MATRIX
Protected Blocks
Unprotected Blocks
Status Register
0
1
Protected
Protected
Protected
Writable
Protected
Writable
DS20002122D-page 16
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MICROCHIP [ MICROCHIP ]
