ML6691
PIN DESCRIPTION
(Continued)
PIN#
NAME
FUNCTION
PIN#
NAME
FUNCTION
20
RXCLK
Receive clock output. Continuous
25 MHz clock provides the timing
reference for the transfer of RXDV,
RXER, and RXD[3:0] to the MAC.
Scrambler/descrambler disable. A
logic high on this input disables the
Stream Cipher scrambler/descrambler.
Ground
Local/remote. A logic low on this input
places the ML6691 in remote mode, in
which the MII interface is disabled at
power on or after a reset operation.
When low, the isolate bit of the
Control register will be set upon power
up or reset.
Reset. A logic high on this input resets
the Status and Control registers to their
default states.
Chip select. A logic low is generated
on this output when the ML6691
detects an address match.
Loopback. A logic low on this output
indicates the loopback function.
Receive symbol clock. A 25 MHz
clock input from the PMD layer. The
rising edge of RXC is used to sample
RSM[4:0].
29-33
RSM[4:0] Receive symbol data inputs. Symbol-
wide (encoded) data from the PMD
layer.
SD
Signal detect. A logic high on this
input indicates the presence of non-
quiet data. The internal signal, linkfail,
is enabled 330µs after SD is asserted.
34
22
DCFR
23
24
GND
LOCAL
35-39
TSM[4:0] Transmit symbol data outputs. Symbol-
wide (encoded) data for transfer to the
PMD layer.
TXC
Transmit symbol clock input. Input
used to generate TXCLK. Use either a
25 MHz crystal or a 25 MHz clock
between TXC input and GND.
Management data input/output. A
bi-directional signal used to transfer
control and status information
between the ML6691 and the MAC.
MDIO is synchronous to MDC.
Management data clock input. A low-
frequency aperiodic clock used as the
timing reference for transfer of
information on the MDIO signal.
40
41
MDIO
25
RST
26
CS
42
MDC
27
28
LPBK
RXC
3
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
