ML65245**/ML65L245*
LATCH
66 MHz
CACHE
(SRAM)
Pentium™ Processor
CONTROL
ADDRESS
DATA
LOCAL BUS
MAIN MEMORY
(DRAM)
CNTL
WE
BWE
PCMC
DATA
LBX
ML65245 BUFFER
MAddr
BMAddr
LBX CNTL
CONTROL
ADDRESS/DATA
PCI™ BUS (33 MHz)
Figure 6. ML65245 in a main memory application for a Pentium based system. The high drive and low propagation
delay are essential to buffer the write enable and memory addresses to the main memory SIIMMs.
CONTROL
CDRAM
or
DRAM
CDRAM
or
DRAM
ADDR
R4X00™
150/75 MHz
ML65245
ML65245
ML65245
CONTROL
MEMORY I/O
CONTROLLER
ADDRESS/DATA
Figure 7. The ML65245 in a non-cache, main memory RISC application. The main memory could be DRAM or
Cache DRAM. The ML65245 can be used as a data I/O transceiver as well as an address buffer, as shown above.
7
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
