ML65245**/ML65L245*
in a dynamic sense. This may be true for CMOS buffer/
line drivers, but it is not true for the ML65245 and
ML65L245. This is because the their sink and source
current capability depends on the voltage difference
between the output and the input. The ML65245 can sink
or source more than 100mA to a load when the load is
switching due to the fact that during the transition, the
FUNCTIONAL DESCRIPTION
The ML65245 and ML65L245 are very high speed non-
inverting transceivers with three-state outputs which are
ideally suited for bus-oriented applications. They provide
a low propagation delay by using an analog design
approach (a high speed unity gain buffer), as compared to
conventional digital approaches. The ML65245 and
ML65L245 follow the pinout and functionality of the
industry standard FCT245 series of transceivers and are
intended to replace them in designs where the
difference between the input and output is large. I is
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only significant as a DC specification, and is 25mA.
ARCHITECTURAL DESCRIPTION
propagation delay is a critical part of the system design
considerations. The ML65245 and ML65L245 are capable
of driving load capacitances several times larger than their
input capacitance. They are configured so that signals
pass from Ai to Bi, or from Bi to Ai, depending on the state
of the T/R pin. All of the signal lines can be made high
impedance via the OE pin.
Until now, buffer/line drivers have been implemented in
CMOS logic and made to be TTL compatible by sizing the
input devices appropriately. In order to buffer large
capacitances with CMOS logic, it is necessary to cascade
an even number of inverters, each successive inverter
larger than the preceding, eventually leading to an inverter
that will drive the required load capacitance at the
required frequency. Each inverter stage represents an
additional delay in the gating process because in order for
a single gate to switch, the input must slew more than half
of the supply voltage. The best of these CMOS buffers has
managed to drive a 50pF load capacitance with a delay of
3.2ns. Micro Linear has produced an octal transceiver
with a delay less than 1.7ns by using a unique circuit
architecture that does not require cascaded logic gates.
The ML65245 uses a feedback technique to produce an
output that follows the input. If the output voltage is not
close to the input, then the feedback circuitry will source
or sink enough current to the load capacitance to correct
the discrepancy.
These unity gain analog buffers achieve low propagation
delays by having the output follow the input with a small
offset. The output rise and fall times will closely match
those of the input waveform. All inputs and outputs have
Schottky clamp diodes to handle undershoot or overshoot
noise suppression in unterminated applications. All
outputs have ground bounce suppression (typically
< 400mV), high drive output capability with almost
immediate response to the input signal, and low output
skew.
The I current drive capability of a buffer/line driver is
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often interpreted as a measure of its ability to sink current
VCC
R8
Q1
Q2
R7
R3
R4
R2
R1
IN
OUT
Q4
Q6
Q5
Q7
Q3
R5
R6
GND
Figure 5. One buffer cell of the ML65245
5
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
