ML6510
ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS
rise time, fall time and duty cycle are measured for a generic load; (see Load Conditions section).
t
R
t
F
f
IN
f
OUT
Rise time, LOAD [0-7] output
Fall time, LOAD [0-7] output
Input frequency, CLK
IN
pin
Output frequency , CLK [0-7]
output
PLL VCO operating frequency
Output duty cycle
Output jitter
Measured at device load, at 1.5V
Cycle-to-cycle
Peak-to-peak
t
LOCK
PLL and deskew lock time
After programming is complete
ML6510-80
ML6510-130 (Note 2)
0.8
→
2.0V, 80MHz
2.0
→
0.8V, 80MHz
150
150
10
10
10
80
40
75
150
11
1500
1500
80
80
130
160
60
ps
ps
MHz
MHz
MHz
MHz
%
ps
ps
ms
f
VCO
DC
t
JITTER
SKEW CHARACTERISTICS
All skew measurements are made at the load, at 1.5V threshold each output load can vary independently
within the specified range for a generic load (see Load Conditions section).
t
SKEWR
t
SKEWF
t
SKEWIO
Output to output rising
edge skew, all clocks
Output to output
falling edge skew
CLK
IN
input to any
LOAD [0-7] output
rising edge skew
Round trip delay CLKX to FBX
pin; output CLK period = t
CLK
Output-to-output rising
edge skew, between matched
loads
Output clock frequency
≥
50MHz
N=M=0
N
≥
2, M
≥
2
Output frequency < 50MHz
Output frequency
≥
50MHz
Providing first (see LOAD
conditions) order matching
order matching between outputs
0
0
250
600
1.25
10
t
CLK
/2
500
1.5
ps
ns
ps
ns
ns
ps
t
RANGE
t
SKEWB
PART-TO-PART SKEW CHARACTERISTICS
Skew measured at the loads, at 1.5V threshold. Reference clock output pins drive clock
input pins of another ML6510.
t
PP1
Total load-to-load skew between
multiple chips interfaced with
reference clock pins.
Total load-to-load skew between
multiple chips interfaced with
reference clock pins.
Slave chip CS = 1, CM = 1 and
N = 0, M = 0; RCLK outputs to
CLK
IN
inputs distance less than 2"
Slave chip CS = 1, CM = 1 and
N
≥
2, M
≥
2; RCLK outputs to
CLK
IN
inputs distance less than 2"
1
ns
t
PP2
1
ns
PROGRAMMING TIMING CHARACTERISTICS
tRESET
t
A1
t
A2
t
A3
t
A4
t
A5
RESET
assertion pulse
width
AUX mode MCLK high time
AUX mode MCLK low time
AUX mode MD
OUT
data
hold time
AUX mode MD
OUT
data
setup time
AUX mode MCLK period
50
2000
2000
10
10
5000
ns
ns
ns
ns
ns
ns
5
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
