ML6510
PIN DESCRIPTION
PIN NUMBER
NAME
DESCRIPTION
32
20
19
21
22
23
28
29
16,14,9,7,
44, 42, 37, 35
18,12,11,5,
2, 40, 39, 33
3,31
25
4, 30, 24
15
8
43
36
17, 13, 10, 6,
1, 41, 38, 34
26
27
ROMMSB
MD
OUT
MD
IN
MCLK
RESET
LOCK
CLK
INH
CLK
INL
CLK[0–7]
FB[0–7]
AVCC[1–3]
AGND[1–3]
DVCC01
DVCC23
DVCC45
DVCC67
DGND[0–7]
RCLKL
RCLKH
MSB of the internal ROM address. Tie to GND if not used. See section on
Programming the ML6510.
Programming pin. See section on Programming the ML6510.
Programming pin. See section on Programming the ML6510.
Programming pin. See section on Programming the ML6510.
Reset all internal circuits. Asserted polarity is low.
Indicates when the PLL and deskew buffers have locked. Asserted polarity is
high.
Input clock pins. For TTL clock reference use CLK
INH
pin
shorted to the CLK
INL
pin. For PECL clock reference drive pins differentially.
Input clock type is selected by the CS bit in the shift register.
Clock outputs
Clock feedback inputs for the deskew buffers
Analog circuitry supply pins, separated from noisy digital supply pins to
provide isolation. All supplies are nominally +5V.
Analog circuitry ground pins
Digital supply pin for CLK0 and CLK1 output buffers. Nominally +5V.
Digital supply pin for CLK2 and CLK3 output buffers. Nominally +5V.
Digital supply pin for CLK4 and CLK5 output buffers. Nominally +5V.
Digital supply pin for CLK6 and CLK7 output buffers. Nominally +5V.
Digital ground pins for CLK [0–7] output buffers. Each clock output buffer has
its own ground pin to avoid crosstalk and ground bounce problems.
Differential reference clock output used to minimize
part-to-part skew when building clock trees with other PACMan
integrated circuits.
3
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
