ML6461
FUNCTIONAL DESCRIPTION
VIDEO TIMING AND INPUTS
The clock source for the ML6461 can be either 27MHz
(CCIR656) or 24.54MHz (NTSC Square Pixel). The
ML6461 internal timing generator also provides necessary
horizontal and vertical syncs, video blanking, burst, and
closed caption timing. The internal clock is derived
through buffering and inverting the external CLK signal.
The inputs YCRCB<7:0>, VSYNC, and HSYNC are
registered at the rising edge of CLK and PHERR is
registered at the falling edge of CLK. All inputs must be
valid for the minimum setup time of 5ns. The outputs
VSYNC, HSYNC, and FIELD are clocked at the rising edge
of CLK and are valid 10ns following the edge of the clock.
The ML6461 can operate in master and slave modes. In
master mode, the ML6461 internally generates the vertical
reset (VSYNC pin is an output) and horizontal reset
(HSYNC pin is an output). In the slave modes, there are
two alternatives. External slave mode allows the user to
provide an external vertical reset (VSYNC pin is an input)
and an external horizontal reset (HSYNC pin is an input).
Internal slave mode (CCIR656) uses the SAV and EAV
codes to generate the vertical and horizontal resets. The
master/slave modes are selected via register program.
Table 3 provides a description of the various modes and
the assignments of the VSYNC, HSYNC, and FIELD pins.
MASTER MODE
A logical 0 in the SLAVE/MASTER bit (bit B28) will
configure the ML6461 in the master mode. Multiplexed Y,
Cr, Cb data is streamed through the YCRCB <7:0> input
pins. VSYNC and HSYNC pins are configured as outputs
and provide vertical and horizontal sync information. The
polarity of the active edge of the HSYNC and VSYNC
pulses can be programmed through the control register via
the SENSE_HSYNC bit (bit B15) and the SENSE_VSYNC
bit (bit B10), respectively. Coincident active edges of the
horizontal and vertical syncs at the start of the line 4
indicates the beginning of an odd field, whereas, the
active edge of the vertical sync pulse when the horizontal
sync is non-active at the middle of line 266, indicates the
beginning of an even field (Figure 1). The FIELD pin can be
configured either as an input or output through the
FRAME_MODE bit (bit B8). If configured as output (B8
=0) it can be set to provide either even/odd field
information (B9 = FLD_FRM_MODE = 0) or analog field
information (B9 = 1). For the former case, a logical 1 on
the FIELD pin indicates odd fields and a logical 0 even
fields. For the latter,(on the FIELD pin), a logical 1 is held
during analog fields 1 and 2, and a logical 0 during analog
fields 3 and 4. If the FIELD pin is configured as an input
(B8 = FRAME_MODE = 1) it must be held low and high on
alternating frames and it should change state at the
beginning of vertical sync during fields 1 and 3. The
internal subcarrier oscillator is reset to make the frame —
for which FIELD pin is held 1 — correspond to analog
fields 1 and 2 (Figure 2). In master mode, a composite
blanking signal is also available thru the HSYNC pin. This
can be activated via the CBLANK bit (B29=1). The
(Continued)
polarity of the composite blanking signal is programmable
from the SENSE_HSYNC bit (B15). When the
SENSE_HSYNC bit is set (B15=1), the ML6461 will output
a logic 0 at the HSYNC pin during the pixels which are
blanked. Conversely, when the SENSE_HSYNC bit is
cleared (B15=0), the ML6461 will output a logic 1 at the
HSYNC pin during the pixels which are blanked.
Consequently, the YCRCB<7:0> inputs will be ignored and
a constant blanking level will be output to the analog
channels YOUT, COUT, and CVOUT. The operation of the
VSYNC and FIELD pins are not affected by the settings of
CBLANK and SENSE_HSYNC.
SLAVE MODES
A logical 1 in the SLAVE/MASTER bit (B28) will configure
the ML6461 for slave mode. Based on what timing
information is provided, there are two slave modes:
internal and external. Composite blanking—similar to that
described in Master Mode—is also available. Note that in
the internal slave mode, vertical and horizontal sync
pulses and/or composite blanking signals are output for
monitoring purposes only. All timing is derived from SAV/
EAV codes.
Internal Slave Mode for CCIR656 with SAV/EAV codes
In this mode (B26 = SLAVE_MODE=1), all the horizontal
and vertical timing information including odd/even field
selection is embedded in the multiplexed Y, Cr, Cb data
stream input through the YCRCB <7:0> pins. VSYNC and
HSYNC pins are configured as outputs to give vertical and
horizontal sync pulses respectively. The operation of the
FIELD pin is similar to that in the master mode. Composite
blanking — similar to the one described in the master
mode — is also available. Note that in the internal slave
mode, vertical and horizontal sync pulses and / or
composite blanking signal is output for monitoring
purposes only. As mentioned above, all timing is derived
from SAV/EAV codes.
External Slave Mode
In this mode: Where (B26 = SLAVE_MODE=0), horizontal
and vertical reset pulses must be provided externally
through HSYNC and VSYNC pins which are configured as
inputs. The polarity of these pulses is programmed
through bits SENSE_HSYNC (B15) and SENSE_VSYNC
(B10). A horizontal reset pulse on the HSYNC pin can be
given either at the beginning of active video
(B25=HRESET_MODE=1) or at the beginning of horizontal
blanking (B25=HRESET_MODE=0). Once per frame, the
active edge of a vertical reset pulse coincident with the
active edge of a horizontal reset pulse initializes the
internal vertical line counter to the beginning of an odd
field at line 4. Non-coincident vertical reset pulses, for
example, the ones which fall outside of the interval (see
Figure 3) determined by the active edge of the horizontal
reset pulse, will be ignored. The FIELD pin, as explained
above can be configured as an input to dictate analog
fields or as an output to monitor odd/even fields or analog
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MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
