ML6461
FUNCTIONAL DESCRIPTION (Continued)
PIXEL SYNCHRONIZATION
proper video location, as well as the proper
demultiplexing of YCrCb values. This synchronization, as
shown in Figures 4 through 5a, is controlled by
SEL_HSYNC1 (B14) and SEL_HSYNC0 (B13). Figures 4
and 4a show synchronization for active edge at the
beginning of active video for positive or negative HSYNC
polarity while Figures 5 and 5a show synchronization for
active edge at the beginning of horizontal blanking for
positive or negative HSYNC polarity.
Master Mode
In this mode, the active edge of horizontal sync pulse
through the HSYNC pin (configured as an output)
indicates the beginning of an active video line (or the
beginning of the horizontal blanking) and the multiplexed
YCrCb pixel data must be synchronized to this edge for
H
FIELD (1,2 and 3,4)
FIELD (ODD/EVEN)
ANALOG FIELDS 1 & 2
ANALOG FIELDS 3 & 4
ANALOG FIELDS 1 & 2
L
H
L
EVEN
EVEN
ODD
EVEN
ODD
ODD
Figure 2a. FIELD Pin Output Summary
active edge of HSYNC
HSYNC
VSYNC
active edge of VSYNC
–32 pixels
64 pixels
coincident interval
for HRESET_MODE=0
active edge of HSYNC
HSYNC
active edge of VSYNC
VSYNC
64 pixels
coincident interval
for HRESET_MODE=1
Figure 3. Coincident Valid Sync Intervals for External Slave Mode
10
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
