ML6401
HC04
+12V
CLOCK IN
R3
500Ω
+
C6
47µF
C5
0.1µF
R8
100Ω
+5V
+
C9
47µF
C10
0.1µF
Q2
Q1
Q3
1175 PINOUT
+
13
14
15
16
17
18
19
20
21
22
23
24
12
C2
10µF
VDD
CLK
CLK
D
A
A
11
VDD
VDD
VDD
O
R10
75Ω
10
D7
D6
D5
D4
D3
D2
D1
D0
MSB
R2
R5
2kΩ
R7*
5kΩ
POT
9
8
7
6
5
4
C1
180Ω
VRTS
VRT
470µF
R4
1kΩ
+
R9
5kΩ
VDD
A
V
IN
VIN+
GND
R1
120Ω
C8
0.1µF
C13
10pF
A
–12V
GND
A
3
+
C3
47µF
C4
0.1µF
VRBS
VRB
LSB
2
1
+
GND
O
C11
0.1µF
C7
47µF
GND
OE
C12
0.1µF
D
*POT R7 WILL HAVE TO BE ADJUSTED
Note:
Circuit in dashed lines is an optional 1175 input
network which can be replaced with circuits in
Figure 1 or 2.
Figure 3. Replacement for 1175.
3. CXD1175 — Connect VRBS to VRB and leave VRTS
open while driving VRT with an external voltage. This
allows similar functionality to #2 preceding, but the
bias voltage (code 0) will move when the full scale
range is changed.
4. CXD1175 — Connect VRTS to VRT and leave VRBS
open while driving VRB with an external voltage. This
allows similar functionality to #2 preceding, but the
bias voltage (code 0) will move when the full scale
range is changed.
ML6401 — Open pin 16, drive pin 17 externally, and
connect pin 22 to pin 23. The full scale range will be
2 × pin 17 volts, and the bias (code 128) will occur at
1.5 volts (internally generated from bandgap). The full
scale range of the A/D must be kept below 4 volts, but
the part is only specified for full scale range of 2 volts.
ML6401 — Connect pin 16 to pin 17, open pin 22 and
drive pin 23 externally. The full scale range will be 2
volts (internally generated from bandgap), and the bias
(code 128) will occur at pin 23 ±2% volts.
7
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
