13
QPO
O (analog)
Charge Pump Output. This output is connected to the external PLL loop
filter. Sources current when the LO frequency is lower than desired.
VREG1
12
QPO
13
9.2Ω
14
VSSPLL
VREG3
19
16
VTUNE
I (analog)
VCO Tuning Voltage. This input from the PLL loop filter determines the
output frequency and is very sensitive to noise coupling and leakage
currents.
VTUNE
16
VREG2
17
10Ω
15
VSSLO
VTXB
24
22
TXISET
I (analog)
A resistor between this pin and ground establishes the PA output power
compression point by setting a bias current.
VCCA
7
TXISET
22
522Ω
2
VSSMX
8
FREF
I (analog)
Input Reference Frequency. Depending on the state of the REFSEL pin
this input is divided by 3 or 4 to generate the PLL reference frequency.
VREG1
12
VCCA
7
FREF
8
2
VSSMX
14
VSSPLL
9
REFSEL
I (CMOS)
Reference Divider Control. If REFSEL is HIGH, FREF is divided by 4,
otherwise FREF is divided by 3. This is a CMOS input, and the
thresholds are referenced to VCCA and VSSMX.
VCCA
7
REFSEL
9
168Ω
2
VSSMX
DS5824-F-01
FINAL DATASHEET
AUGUST 2004
8
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
