SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RRFIF
Transmit IF feed thru
Measured at TXO port with CW signal at
FTXI and PTXI
-30
dBc
R2LO
Transmit 2xLO feed thru
See Note 1
Measured at TXO port with CW signal at
FTXI and PTXI
<-30
<-20
<-20
dBc
dBc
dBc
R3LO
R4LO
Transmit 3xLO feed thru
See Note 1
Measured at TXO port with CW signal at
FTXI and PTXI
Transmit 4xLO feed thru
See Note 1
Measured at TXO port with CW signal at
FTXI and PTXI
RTSB
RMXN
Transmit lower sideband rejection
From TXI to TXO ports at PTXI for
FTXO= 835-960MHz
25
dBc
dBc
Mixer products rejection at output port
See Note 1
From TXI to TXO ports at PTXI for
FTXO= 960-970MHz
>55
INTERFACE LOGIC LEVELS
Input pins (XCEN, TXON, RXGN, REFSEL)
VCCA*0.7
-0.4
VCCA+0.4
VCCA*0.3
5
VIH
VIL
IB
Input high voltage
Input low voltage
Input bias current
Input capacitance
V
V
All states
-5
µA
pF
CIN
1MHz test frequency
4
Note 1: Typical specs represent a 3 sigma data point at sample test.
PIN DESCRIPTIONS
PIN
NAME
I/O
FUNCTION
DIAGRAM
POWER & GROUND
2
7
VSSMX
VCCA
GROUND
POWER
GROUND
GROUND
INPUT
Mixer Ground
N/A
N/A
N/A
N/A
N/A
N/A
Regulated External Supply, Requires Proper Decoupling Components
PLL Ground
14
15
24
X
VSSPLL
VSSLO
VTXB
VCO and LO Ground
TX Buffer Supply Voltage, Connect to Pin 7
Exposed Paddle. Ground/Return
VSSDB
GROUND
SUPPLY REGULATION
1
VMIX
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
2.7V Supply Decoupling Point, Connect to Pin 26
2.7V Regulated Supply Output
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12
17
18
19
25
26
28
VREG1
VREG2
VBG2
2.5V Regulated Supply Output
1.24V Bandgap2 Supply Decoupling Point
2.7V Regulated Supply Decoupling Point
1.24V Bandgap1 Supply Decoupling Point
2.7V Regulated Supply Output, Connect to Pins 1 and 28
2.7V LNA Supply Decoupling Point, Connect to Pin 26
VREG3
VBG1
VREG4
VLNA
DS5824-F-01
FINAL DATASHEET
AUGUST 2004
5
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
