ML4900
5V
IN
12V
IN
OUTEN
UP#
D1
BAW56
C11
22µF
25V
C10
220nF
16V
C13
1µF
16V
R5
100kΩ
R4
1kΩ
C12
220nF
16V
ML4900
1
2
3
4
5
3X C1
1800µF
10V
C2
C3
VID0
VID1
VID2
VID3
PWRGD
C8
220nF
16V
D0
D1
D2
D3
SHDN
PWR GOOD
VREF
GND
PROTECT
16
VDD
15
N DRV H
14
N DRV L
13
PWR GND
12
COMP
11
ISENSE
10
VFB
9
R3
330kΩ
C9
33pF
Q2
R1
5mΩ
1W
4X C4
1800µF
10V
C5
C6
C7
Q1
L2
1.4µH
V
CC
P
6
7
8
V
SS
Figure 1. Pentium Pro VRM Circuit
and GND pins. At the same time, PWR GND must have a
low impedance connection to the ground plane used on
the board, as high instantaneous currents will flow in PWR
GND when N DRV L and N DRV H switch the capacitive
loads of the output MOSFET gates. A layout technique
which satisfies these requirements is to return PWR GND
to the grounded end of R1 using a high current Kelvin
connection. Figure 2 shows one successful
implementation of these PCB layout requirements.
I
SENSE
is an input to a medium-speed, high-sensitivity
comparator. It is often helpful to shield the trace running
from R1 to I
SENSE
with a “guard trace” connected to circuit
ground.
The compensation components R3 and C9 are high-
impedance nodes connected to the output of the voltage
loop error amplifier. These components should be kept in
close proximity to the ML4900. C9 should be returned to
GND, not to PWR GND or the ground plane of the PC
board. It may be helpful to shield the trace running from
R3 to COMP with a “guard trace” connected to circuit
ground.
Keep the V
REF
bypass capacitor C8 close to the ML4900.
Ensure that its ground connection is to GND, not PWR
GND or the ground plane of the PCB.
The V
DD
bypass capacitors C10 and C11 should be
returned to PWR GND or to the PC board ground plane.
They should not be returned to GND due to high transient
currents which could interfere with the current sensing
function.
In order to reduce circuit size, complexity, and cost, direct
drive of all N-channel power MOSFETs in the output stage
is employed, derived from the 12V input bus. This delivers
at least 10V of V
GS
enhancement to the MOSFET(s)
performing the synchronous rectification function. The
power switching MOSFET(s), however, have a worst-case
V
GS
enhancement of about 6V, and must therefore be
logic-level parts.
If a given design uses power MOSFETs in an 8 pin SOIC
package style, keep in mind that the thermal dissipation
capability of these parts is largely dictated by the copper
area available to their drains. A good layout will maximize
this area.
TO
SYNCHRONOUS
RECTIFIER
MOSFET
SOURCE
TO
ISENSE
TO
PWR GND
TO
GND
SENSE
RESISTOR
POWER GROUND RETURN
(GROUND PLANE)
Figure 2. Kelvin Sense Connections
7
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
