ML4900
PIN CONFIGURATION
ML4900
16-Pin Narrow SOIC (S16N)
D0
D1
D2
D3
SHDN
PWR GOOD
VREF
GND
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
PROTECT
VDD
N DRV H
N DRV L
PWR GND
COMP
ISENSE
VFB
D0
D1
D2
D3
NC
SHDN
NC
PWR GOOD
VREF
GND
ML4900
20-Pin TSSOP (T20)
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
PROTECT
VDD
NC
N DRV H
N DRV L
PWR GND
NC
COMP
ISENSE
VFB
PIN DESCRIPTION
(Pin Number in Parentheses is for TSSOP Version)
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1 (1)
2 (2)
3 (3)
4 (4)
5 (6)
6 (8)
D0
D1
D2
D3
SHDN
PWR GOOD
LSB input to the DAC which sets
the output voltage
Input to the DAC which sets the
output voltage
Input to the DAC which sets the
output voltage
MSB input to the DAC which sets
the output voltage
Grounding this pin shuts down the
regulator
This open collector output goes
low whenever
SHDN
goes low or
when the output is not within
+10% of its nominal value
Bypass connection for the internal
3.5V reference
8 (10)
9 (11)
GND
V
FB
Analog signal ground
Output voltage feedback pin
Current sense input
Connection for the compensation
and optional soft-start delay
network
Power ground
Synchronous rectifier driver output
Buck switch driver output
12V power supply input
Connection for the integrating
current limit network and the
UVLO monitor for the 5V supply
10 (12) I
SENSE
11 (13) COMP
12 (15) PWR GND
13 (16) N DRV L
14 (17) N DRV H
15 (19) V
DD
16 (20) PROTECT
7 (9)
V
REF
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
