ML4841
FUNCTIONAL DESCRIPTION (Continued)
LEADING/TRAILING MODULATION
Generating V
CC
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.
The ML4841 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the
voltage internal to the part at 13.5V. This allows a low
power dissipation while at the same time delivering 10V
of gate drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying it. This can be easily done with
a single resistor in series with the Vcc pin, returned to a
bias supply of typically 18V to 20V. The resistor’s value
must be chosen to meet the operating current requirement
of the ML4841 itself (19mA max) plus the current required
by the two gate driver outputs.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.
EXAMPLE:
With a V
of 20V, a V limit of 14.6V (max) and
CC
BIAS
driving a total gate charge of 100nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:
One of the advantages of this control technique is that
it requires only one system clock. Switch 1 (SW1) turns
off and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.
IGATEDRIVE = 100kHz × 45nC + 200kHz ×52nC = 15mA
(12)
(13)
(
)
(
)
20V −14.6V
19mA +15mA
R
BIAS
=
= 160Ω
To check the maximum dissipation in the ML4841, check
the current at the minimum V (12.4V):
CC
20V −12.4V
I
CC
=
= 47.5mA
(14)
160Ω
The maximum allowable I is 55mA, so this is an
CC
acceptable design.
The ML4841 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.
SW2
I2
I3
I4
L1
I1
+
VIN
RAMP
VEAO
RL
SW1
DC
C1
REF
U3
EA
+
TIME
–
DFF
VSW1
+
–
R
D
RAMP
CLK
Q
U1
U2
OSC
U4
Q
CLK
TIME
Figure 4. Typical Trailing Edge Control Scheme
11
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
